1. Field of the Invention
The field of the invention is data processing, or, more specifically, methods, apparatus, and products for maintaining cache coherence in a multi-node, symmetric multiprocessing (‘SMP’) computer.
2. Description of Related Art
Contemporary high performance computer systems, such as, for example, the IBM System z series of mainframes, are typically implemented as multi-node, symmetric multiprocessing (‘SMP’) computers with many compute nodes. SMP is a multiprocessor computer hardware architecture where two or more, typically many more, identical processors are connected to a single shared main memory and controlled by a single operating system. Most multiprocessor systems today use an SMP architecture. In the case of multi-core processors, the SMP architecture applies to the cores, treating them as separate processors. Processors may be interconnected using buses, crossbar switches, mesh networks, and the like. Each compute node typically includes a number of processors, each of which has at least some local memory, at least some of which is accelerated with cache memory. The cache memory can be local to each processor, local to a compute node shared across more than one processor, or shared across nodes. All of these architectures require maintenance of cache coherence among the separate caches.
In a traditional strong store ordered, symmetric multiprocessing computer system composed of many compute nodes, with the compute nodes interconnected through a given bus topology, with a coherence protocol that exchanges address, data, and coherency information, the release of a cache line and system resources by the protocol for completion of a memory/cache to cache operation does not occur until after a protracted series of communications is completed, including confirmation from all other caches on the other nodes that those caches have completed all coherency operations according to the protocol. Waiting for such confirmation before releasing the cache line and system resources represents additional latency in memory operations. In addition, in traditional protocols, even if the requesting node releases the line before receiving full confirmation, such protocols include additional communications regarding coherence state from the requesting node to the other nodes. Such additional communications represent additional latency in that the other nodes cannot be relied upon for additional coherency operations until all such confirmations are received by the requesting node.